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Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
FEATURES
* 2 differential 2.5V/3.3V LVPECL / ECL outputs * 1 CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency up to 1GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 15ps (maximum) * Part-to-part skew: 100ps (maximum) * Propagation delay: 1.4ns (maximum) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS85311 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V ECL/ HiPerClockSTM LVPECL Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.T h e ICS85311 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and partto-part skew characteristics make the ICS85311 ideal for those clock distribution applications demanding well defined performance and repeatability.
,&6
BLOCK DIAGRAM
CLK nCLK Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc CLK nCLK VEE
ICS85311
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
ICS85311AM
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1
REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
Type Output Output Power Input Input Power Pullup Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Connect to ground. Inver ting differential clock input. Positive supply pin. Connect to 2.5v or 3.3V. Pulldown Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE nCLK CLK VCC
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor CLK, nCLK 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 112C/W -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 25 Units V mA
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltag for CLK, nCLK is VCC + 0.3V.
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 25 Units V mA
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
Test Conditions CLK nCLK CLK nCLK VCC = VIN = 2.625V VCC = VIN = 2.625V VCC = 2.625V, VIN = 0V VCC = 2.625V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.5V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltag for CLK, nCLK is VCC + 0.3V.
TABLE 3E. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, VCC = 2.5V5%, TA = 0C TO 70C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4F. AC CHARACTERISTICS, VCC = 3.3V5%, VCC = 2.5V5%, TA = 0C TO 70C
Symbol fMAX Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 1GHz 0.9 Test Conditions Minimum Typical Maximum 1 1.4 15 100 700 700 52 Units GHz ns ps ps ps ps %
tPD tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle 48 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2.0V
nQx
VEE = -1.3V 0.135V
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
VCC
SCOPE
Qx
LVPECL
VCC = 2.0V
nQx
VEE = -0.5V 0.125V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
V CC
CLK
V
nCLK
PP
Cross Points
V
CMR
VEE
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 3 - OUTPUT SKEW
Qx PART 1 nQx
Qy PART 2 nQy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
80% 80% V 20% 20% t t
AND
SWING
Clock Inputs and Outputs
R
F
FIGURE 5 - INPUT
OUTPUT RISE
AND
FALL TIME
CLK
nCLK
Q0 - Q1 nQ0 - nQ1
t
PD
FIGURE 6 - PROPAGATION DELAY
CLK, Qx nCLK, nQx
Pulse Width t t odc = t
PW PERIOD
PERIOD
FIGURE 7 - odc & tPERIOD
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
VCC
CLK_IN
CLK_IN
R1 1K R1 1K V_REF
V_REF
+
+
-
C1 0.1uF C1
0.1uF
R2 1K R2 1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85311. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation of the ICS85311 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core) = VCC * IEE = 3.465V * 25mA = 86.6mW Power (outputs) = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 x 30.2mW = 60.4mW
Total Power (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. In order to determine if the junction temperature is below 125C, the appropriate junction-to-ambient thermal resistance JA must be used in conjunction with the total power dissipation. Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per the table below: Tj = JA * Pd_total + TA where Pd_total is the total power dissipation of the device and TA is the ambient temperature. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.147W * 103.3C/W = 85.2C. This is well below the limit of 125C. This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply voltage, air flow, and the type of board (single layer or multi-layer). Thermal Resistance q for 8-pin SOIC, Forced Convection
JA
q by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
0 153.3C/W 112.7C/W
200 128.5C/W 103.3C/W
500 115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
VOUT RL 50 VCC - 2V
Figure 9 - LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V Pd_L = [(V * (V - 2V))/R ]*(V - V
CC L CC CC L CC
OH_MAX
OH_MAX
)
OL_MAX
(V - 2V))/R ]*(V - V =V
OL_MAX
)
For logic high , V
CC
OUT
OH_MAX
=V
CC
1.0V = 2.465V
Using V = 3.465, this results in V * For logic low , V
CC OUT
OH_MAX
=V
OL_MAX
= V 1.7V
CC OL_MAX
Using V = 3.465, this results in V
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50 ]*(3.465V - 2.465V) = 20.0mW Pd_L = [(1.765V - (3.465V - 2V))/50 ]*(3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
0 153.3C/W 112.7C/W
200 128.5C/W 103.3C/W
500 115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85311 is: 225
ICS85311AM
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REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
PACKAGE OUTLINE - M SUFFIX
N
C
8
5
E
1 4
H
L
D A2 A
hx45
e B
A1
SEATING PLANE
.10 (.004)
TABLE 6. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 1.25 0.33 0.19 4.80 3.80 1.75 0.25 1.50 0.51 0.25 5.00 4.00 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN MAXIMUM 8 0.532 0.0040 0.0492 0.013 0.0075 0.1890 0.1497 0.0688 0.0098 0.0590 0.020 0.0098 0.1968 0.1574 Inches MINIMUN MAXIMUM
0.050 BASIC 0.2284 0.010 0.016 0 0.2440 0.020 0.050 8
Reference Document: JEDEC Publication 95, MS-012
ICS85311AM
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12
REV. A JUNE 29, 2001
Integrated Circuit Systems, Inc.
ICS85311
Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
Marking ICS85311AM ICS85311AM Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature 0C to 70C 0C to 70C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS85311AM ICS85311AMT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS85311AM
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REV. A JUNE 29, 2001

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